ASIC RTL Design Engineer

Position: ASIC RTL Design Engineer Experience: 8 Years Location: Noida Share resume on medha.gaur@einfochips.com Key Responsibilities Develop synthesizable RTL from micro-architecture specifications. Design digital blocks such as control logic, datapath, and bus interfaces (AXI/AHB/APB). Debug and validate RTL using simulation and waveform analysis. Collaborate with verification teams for functional validation. Support RTL synthesis, timing closure, and integration at SoC level. Maintain design…