Lead RTL Design Engineer

Lead RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 6 to 9 Years Job Description 6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable. Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture & designing cores and ASICs. Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Pow…